The Apple
*SPICE Netlist generated by Advanced Sim server on 2022-10-26 2:57:15 PM
*.options MixedSimGenerated

*Schematic Netlist:

CC39 NetC39_1 NetC39_2 100n
LL5 NetL5_1 0 1m
XQ13 NetQ13_5 NetQ13_4 NetC39_2 BUK
XQ14 NetQ13_5 NetQ13_4 NetC39_2 BUK
XQ15 NetC39_2 NetQ15_4 0 BUK
XQ16 NetC39_2 NetQ15_4 0 BUK
RR21 NetQ13_4 NetC39_2 4.7k TC1=0 TC2=0
RR22 NetQ15_4 0 4.7k TC1=0 TC2=0
RR23 NetC39_2 NetL5_1 0.2 TC1=0 TC2=0
XU14 NetC39_1 NetU14_7 NetQ13_4 NetC39_2 NetU14_8 NetQ15_4 NetU14_1 0 UCC27211
VV1 NetQ13_5 0 12 AC 1 0
VV2 NetU14_1 0 42 AC 1 0
VV3 NetU14_7 0 DC 0.2 PULSE(0 5 0 10n 10n 400n 0.8u 0) AC 1 0
VV4 NetU14_8 0 DC 0.2 PULSE(0 5 0.4u 10n 10n 400n 0.8u 0) AC 1 0

*.PROBE {V(NetU14_8)} =PLOT(1) =AXIS(1) =UNITS(V)
*.PROBE {V(NetU14_7)} =PLOT(1) =AXIS(1) =UNITS(V)
*.PROBE {V(NetC39_2)} =PLOT(1) =AXIS(1) =UNITS(V)

*Functions because ngspice is for old people lol
*.func if(a,b,c) 'ternary_fcn( a , b , c )'

*Selected Circuit Analyses:
*.TRAN 10n 0.1m 0 10n

*Models and Subcircuits:
.SUBCKT BUK DRAIN GATE SOURCE
LD DRAIN 5 2e-11
RLD2 DRAIN 5 0.0502654824574367
RLD1 5 4 5e-06
LG GATE 1 7.81292696075128e-10
RLG GATE 1 1.96360271543439
LS SOURCE 8 6.3e-10
RLS2 SOURCE 8 1.58336269740926
RLS1 8 7 0.00024
RDS 7 4 10000000 TC=-0.005
RS 6 7 0.0001
RD 3 4 0.0133151139290286 TC=-0.0781572632359099,0.00198513411700269
RBD 9 4 0.00089496402324299 TC=-0.0781572632359099,0.00198513411700269
DBD 7 9 DBD
M1 3 2 6 6 MINT
RGS 2 6 200000000
CGS 2 6 3.681e-09
RG 1 2 2.14052
* CGD
C11    11   12   1E-12
V11    11   0   0Vdc
V1    16   17 V(13,0)
G11    3 2  16  17 VALUE { V(13, 0)*I(V11) }
E11    12   0  3 2  1
E12    13   0 16 17 TABLE {V(12)}
+ -20   2492
+ -16   2491
+ -10   2486
+ -5    2471
+ -4    2463
+ -3    2438
+ -2    2124
+ -1    2661
+ -0.5  1896
+ -0.2  1284
+ -0.1  1114
+ 0 973.5
+ 0.1   843
+ 0.2   753
+ 0.5   610
+ 1 496
+ 2 362
+ 3 304
+ 4 277
+ 5 257
+ 6 240
+ 8 214
+ 10    195
+ 12    181
+ 15    165
+ 20    146
+ 30    120
+ 50    95
.MODEL MINT NMOS(Vto=2.16761607523833 Kp=3.756407e+002 Nfs=430000000000 Eta=0
+ Level=3 L=1e-4 W=1e-4 Gamma=0 Phi=0.6 Is=1e-24
+ Js=0 Pb=0.8 Cj=0 Cjsw=0 Cgso=0 Cgdo=0 Cgbo=0
+ Tox=1e-07 Xj=0
+ U0=600 Vmax=1000)
.MODEL DBD D(Bv=110 Ibv=2.500000E-004 Rs=1E-6 Is=1.16152188652576e-12
+ N=1 M=0.59 VJ=0.58 Fc=0.5 Cjo=8.23e-10 Tt=2.856e-08)
.ENDS

*$
.model NMOS01 NMOS
+ VTO = 3
+ KP = 2.25
+ LAMBDA = 0.001
+ RS = 1m

*$
.model PMOS01 PMOS
+ VTO = -1
+ KP = 0.46
+ LAMBDA = 0.001
+ RS = 1m

*$
.model DIODE01 D
+ IS = 1.038e-15
+ N = 1
+ TT = 20e-9
+ CJO = 5e-12
+ RS = 0.50
+ BV = 130

***
*$
*  UCC27211 Model
*****************************************************************************
*  (C) Copyright 2011 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warrenties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose.  The model is
** provided solely on an "as is" basis.  The entire risk as to its quality
** and performance is with the customer
*****************************************************************************
*
** Released by: Analog eLab Design Center, Texas Instruments Inc.
* Part: UCC27211
* Date: 11/16/2011
* Model Type: TRANSIENT
* Simulator: PSPICE
* Simulator Version: 16.0.0.p001
* EVM Order Number: None
* EVM Users Guide: None
* Datasheet: SLUSAT7 - November 2011
*
* Model Version: Final 1.00
*
*****************************************************************************
*
* Updates:
*
* Final 1.00
* Release to Web.
*
*****************************************************************************
* source UCC27211
.SUBCKT UCC27211
+ HB
+ HI
+ HO
+ HS
+ LI
+ LO
+ VDD
+ VSS
V1    16   17 1vdc
C_U7_C4 HS HO 1pF
E_U7_E1 U7_N208620 HO 16 17
+ VALUE { IF(V(U7_N208706, 0) > 0.5, 5, -5) }
C_U7_C3 HO U7_N208506 20p
C_U7_C5 HO HB 1pF
R_U7_R4 HB U7_N208424 .2
M_U7_M1 U7_N208424 U7_N208506 HO HO NMOS01
*+ L=10u
*+ W=10u
M_U7_M2 U7_N208826 U7_N208506 HO HO PMOS01
R_U7_R5 U7_N208826 HS .2
R_U7_R3 U7_N208506 U7_N208620 100
C_U7_C1 U7_N208506 U7_N208424 7p
C_U7_C2 U7_N208826 U7_N208506 7p
X_U7_U1 H_DRV U7_N208706 DELAY 
*PARAMS: RINP=1K DELAY=16n
C_U8_C4 VSS LO 1pF
E_U8_E1 U8_N208620 LO 16 17
+ VALUE { IF(V(U8_N208706, 0) > 0.5, 5, -5) }
C_U8_C3 LO U8_N208506 20p
C_U8_C5 LO VDD 1pF
R_U8_R4 VDD U8_N208424 .2
M_U8_M1 U8_N208424 U8_N208506 LO LO NMOS01
*+ L=10u
*+ W=10u
M_U8_M2 U8_N208826 U8_N208506 LO LO PMOS01
R_U8_R5 U8_N208826 VSS .2
R_U8_R3 U8_N208506 U8_N208620 100
C_U8_C1 U8_N208506 U8_N208424 7p
C_U8_C2 U8_N208826 U8_N208506 7p
X_U8_U1 L_DRV U8_N208706 DELAY 
*PARAMS: RINP=1K DELAY=16n
G_U3_G1 HB HS H_ENB 0 65u
V_U3_V1 U3_N00585 HS 6.7Vdc
V_U3_V2 U3_N00613 0 1.1Vdc
X_U3_U1 H_ENB HB U3_N00585 U3_N00613 COMP_BOB
R_U1_R1 VSS HI 70k
C_U1_C1 VSS HI 2p
X_U1_U1 H_INP HI U1_N02053 U1_N02141 COMP_BOB
R_U1_R2 VSS VDD 1G
V_U1_V1 U1_N02053 VSS 2.3Vdc
V_U1_V2 U1_N02141 0 0.7Vdc
G_U4_G1 VDD VSS L_ENB 0 80u
V_U4_V1 U4_N00415 VSS 7.0Vdc
V_U4_V2 U4_N00435 0 0.5Vdc
X_U4_U1 L_ENB VDD U4_N00415 U4_N00435 COMP_BOB
R_U2_R1 VSS LI 70k
C_U2_C1 VSS LI 2p
X_U2_U1 L_INP LI U2_N02053 U2_N02141 COMP_BOB
R_U2_R2 VSS VDD 1G
V_U2_V1 U2_N02053 VSS 2.3Vdc
V_U2_V2 U2_N02141 0 0.7Vdc
X_U6 L_INP L_ENB L_DRV AND2
D_D1 VDD HB DIODE01
X_U5 H_ENB H_INP L_ENB H_DRV AND3
.ENDS UCC27211

*$
.SUBCKT AND2 A B Y
V1 4 5 1vdc
EINT YINT 0 4 5 VALUE {IF(V(A) > 0.5 && V(B) > 0.5, 1, 0)}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND2

*$
.SUBCKT DELAY INP OUT 
*PARAMS: RINP = 1k DELAY = 10n
R1 INP 101 1k
V1 14 15 1
C1 101 102 0.00014427n
E1 102 0 OUT 0 0.5
E2 103 0 14 15 VALUE {IF(V(101) > 0.5, 1, 0)}
R2 103 OUT 1
C2 OUT 0 1n
.ENDS DELAY

*$
.SUBCKT COMP_BOB Y VINP VINN VHYS
V1 14 15 1
EINT YINT 0 14 15
+ VALUE { MAX(0, MIN(1, 1000*(5e-4 + V(Y)*V(VHYS) + V(VINP) - V(VINN)))) }
RINT YINT Y 1
CINT Y 0 1n
.ENDS COMP_BOB

*$
.SUBCKT AND3 A B C Y
V1 14 15 1
EINT YINT 0 14 15
+ VALUE {IF(V(A) > 0.5 && V(B) > 0.5 && V(C) > 0.5, 1, 0)}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND3

.END